The present invention relates generally to semiconductor devices and, more particularly, to non-volatile memories and isolated channel programming and array operation.
Conventional memory arrays, such as an electrically erasable programmable read only memory (EEPROM) array, comprise pluralities of individual memory cells. The memory cells can be programmed for desired logic or memory states. In programming the array, each cell must have either a high or low voltage (i.e., on or off) state. The high voltage state that is desirable is limited by power consumption considerations and physical and materials constraints. The low voltage state that is desirable is likewise limited because it must be differentiated from the high voltage state and, yet, it must not result in cross leakage among neighboring cells in tight memory array cell distributions. The higher the voltage required for accessing the low states, the greater the power consumed by the memory cells.
Conventionally, memory cells are distributed in an array. A simplified example of such an array is shown in FIG. 1. The example array in FIG. 1 includes only nine individual memory cells, whereas typical memory arrays include many more cells. The small number of cells in the example array of FIG. 1 is, therefore, to be understood as merely exemplary for purposes of illustration and discussion herein. In practice, the same principles described herein are applicable to memory arrays of widely varying size, including much larger arrays of memory cells.
The array of FIG. 1 includes individual memory cells, for example, memory cells 101-109. Each cell of the array, such as, for example, cell 101, is connected with a wordline at its gate, such as wordline (W1) 121 connected to cell 101 at its gate. Other cells 102 and 103, for example, are also connected to the wordline 121. For reference purposes in FIG. 1, the cells 101, 102, 103 are distributed within the array in a common xe2x80x9crowxe2x80x9d. Common wordlines, such as wordlines (W1) 121, (W1) 122, and (W3) 123, connect cells in common rows, such as cells 101, 102, 103, and 104, 105, 106, and 107, 108, 109, respectively.
A drain of each cell of the row is connected to a separate bitline, for example, the drain of cell 101 is connected to bitline (B1) 131. The same bitline 131 connects with other cells 104 and 107, for example, of the array. For reference purposes, the cells 101, 104, 107 are distributed in a common xe2x80x9ccolumnxe2x80x9d of the array. Common bitlines, such as bitlines 131, 132, and 133, connect cells 101, 104, 107 and 102, 105, 108 and 103, 106, 109, respectively, in common columns.
A source of the cell 101 is connected to a source line 125. This source line 125 also connects the source of all other cells 101-109 of the entire array. Thus, it can be understood in FIG. 1, that respective ones of the parallel wordlines 121-123 connect the gate of each of the cells 101-103, 104-106, or 107-109, respectively, distributed in common rows of the array, and whereas respective ones of the parallel bitlines 131-133 connect the drain of each of the cells 101,104,107, or 102,105,108, or 103,106,109, respectively, distributed in common columns of the array. All cells 101-109 of the array are situated in a common well, for instance, a p-well 100 of FIG. 1. In this arrangement, each of the source line 125 and the p-well 100 are common to each of the cells 101-109 of the array.
In programming the foregoing array of cells 101-109, a positive voltage is applied to selected memory cell wordlines and to the selected memory cells bitlines. The selected memory cells are subsequently programmed via hot carrier injection (HCI) thereby altering the threshold voltage of selected memory cells (i.e. altering the amount of charge stored in their floating gates). The change in threshold voltage is periodically sensed during the programming event to detect whether or not a targeted threshold voltage has been achieved for all selected memory cells in the array. In erasing the foregoing array of cells 101-109, the entire array is erased by applying a negative voltage to each wordline and a positive voltage to either the source line 125 or to the common p-well 100. In this manner, the floating gates for all memory cells in the array will correspondingly be charged the low threshold voltage state, simultaneously.
Referring to FIG. 2, a plot illustrates threshold voltage among bits represented by memory cells 101-109 of the array under a high threshold voltage state and low threshold voltage state, i.e., corresponding to xe2x80x9coffxe2x80x9d or xe2x80x9conxe2x80x9d states. It is notable that each of the high voltage state and the low voltage state is actually a range of voltage levels in the vicinity of a particular target high voltage and target low voltage, respectively. The ranges of voltage exhibited in FIG. 2 are illustrative of the type of distribution which is exhibited on programming of the conventional array in which all cells share a common well, such as p-well 100. In the distribution of FIG. 2, high threshold voltages are concentrated in a relatively narrow distribution between, for example, 5 to 6 volts. However, the threshold voltage distribution will be much broader for the low threshold voltage state, such as 0.5 volts to 2.5 volts. This broader threshold voltage distribution at the lower threshold voltage state results mainly because all memory cells are erased at the same time as a result of the common p-well in which all the bit cells are located. The process variation, materials defects, and degradation of material properties are all major causes of this broader Vt distribution at the lower threshold state in comparison with the higher threshold state. The wider Vt distribution leads to the requirement of high wordline voltage during read operations, to ensure success of read access of the low Vt state bit cells.
The problems presented include that substantial power is consumed by the requirement of higher wordline voltage to assure achievement of the read access of the low threshold state. Furthermore, to achieve higher wordline voltage, a boost from a low voltage power supply can be required in order to achieve the desired wordline voltage. To reach the desired wordline voltage, even with the boost from the low voltage power supply, can typically require significant amounts of time because of slow boosting if only low power is employed. It would be an advantage to control the voltage range distributions among cell arrays at the lower threshold voltage levels, in order to reduce the required wordline voltage for read access. Controlling the lower voltage range distributions, however, can lead to problems of cross leakage among neighboring cells when all cells of the array are located in a common p-well.
The present invention is a significant improvement and advantage in the art and technology because it provides for limiting lower threshold voltage distributions to a narrower range and further enables faster access by using lower wordline voltage.